Helical Interleaving For Burst Error Correction Enhancement of Turbo Product Codes

1999, Efficient Channel Coding, Inc. Helical Interleaving for Burst Error Correction Enhancement of Turbo Product Codes ECC has developed a helical interleaving technique that increases the burst error correction capability of TPCs. The burst error correction capabilities of the resulting TPCs is quite dramatic. In this note, we provide some simulation results to quantify this for the (4096,3249) TPC as well as the (4096,1311) TPC. At the encoder, helical interleaving defines the order in which bits from an encoded block of data are read out to the modulator. At the receiver, helical deinterleaving defines the order in which bits from the demodulator are read into the decoder. Figure 1 illustrates the helical interleaving process for the two dimensional (4096,3249)TPC. The first bit (labeled bit 0) to be read out of the encoder is in the upper left-hand corner of the array. The second bit is from the second row, second column, the third bit is from the third row third column and so on diagonally until the lower right hand corner is reached. Then, the 65 bit is the first row in the second column. This process continues until the last bit (the 4096 bit) is read from the array. Thus, when the last row is reached, wrap around to the first unread row. Similarly, when the last column is reached wrap around to the first unread column. Helical interleaving in the three dimensional codes follows the same logic except that instead of reading diagonally through an array of data, we read diagonally through a cube of data.